A High-Order-N Frequency-Multiplier Using Pulsed Oscillator: Modeling and Optimization
- 13 June 2021
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Abstract
This work focusses on the modeling of the Phase Noise (PhN) through the building blocks of a high-order-N frequency multiplication circuit that uses Pulsed injection Locking Oscillator (P-OSC). The proposed analytical expressions allow predicting the transformation of PhN through different blocks of the frequency multiplier. To cope with the inherent nonlinear characteristics of frequency multiplication circuits, simplified nonlinear equivalent circuits (NEC) are used to loosen the time and memory constraints of the numerical simulations. The analytical results show good agreements with Harmonic Balance simulations of NEC. This work helps determining the circuit key parameters controlling Phase Noise and output integrated RMS Jitter for optimization purposes.Keywords
This publication has 6 references indexed in Scilit:
- Lock Detector Integrated in a High Order Frequency Multiplier Operating at 60-GHz-Band in 45nm CMOS SOI Technology2020
- A Multichannel Programmable High Order Frequency Multiplier for Channel Bonding and Full Duplex Transceivers at 60 GHz Band2020
- A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave ApplicationsIEEE Journal of Solid-State Circuits, 2015
- A simple, unified phase noise model for injection-locked oscillators2011
- A study of injection locking and pulling in oscillatorsIEEE Journal of Solid-State Circuits, 2004
- The Nonlinear Theory of Electric OscillationsProceedings of the IRE, 1934