Ziyao Yang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Ziyao Yang has a total of 11 co-authors. Here are the top co-authors by number of shared publications:
- Yu Cao
University of Minnesota
2 shared publications Amol D. Gaidhane
1 shared publication- Amol Domaji Gaidhane
Arizona State University, Tempe, AZ, United States
1 shared publication Frank Liu
1 shared publicationGlenn Workman
GLOBALFOUNDRIES, Austin, TX, USA
1 shared publicationJán Drgoňa
1 shared publication
Latest Publications
- 5 March 2026
- Published by Elsevier in Solid-State Electronics
- Vol. 234
Continual graph learning for physics-constrained CMOS transistor models
- 5 March 2026
- Published by Elsevier in Solid-State Electronics
- Vol. 234
Continual graph learning for physics-constrained CMOS transistor models
- Open Access
- 1 February 2024
- Published by Elsevier in Energy and AI
- Vol. 16
Physics-constrained graph modeling for building thermal dynamics
- 1 February 2024
- Published by Elsevier in Energy and AI
- Vol. 16
Open AccessPhysics-constrained graph modeling for building thermal dynamics
- 6 November 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 71 (1) , 254-262
Graph-Based Compact Model (GCM) for Efficient Transistor Parameter Extraction: A Machine Learning Approach on 12 nm FinFETs
Compact models for CMOS transistors usually have many fitting parameters to accurately capture the device properties, especially for the cutting-edge CMOS technology. As a result, parameter extraction of compact models requires a lot of expertise and engineering time. To overcome this barrier, we propose a new machine learning approach, graph-based compact model (GCM), to automate parameter extraction with high efficiency. GCM starts from a core set of physical equations, such as long-channel surface potential with semi-empirical analytic equations for short-channel effects. It then aggregates these physical models through graph neural networks (GNNs) to predict the final device behavior. In this approach, the analytic equations preserve physical dependencies on process and bias conditions, while the neural networks in GCM enable model training driven by a small set of measurement data. Using GCM, we demonstrate parameter extraction with high accuracy for dc and ac data from GlobalFoundries 12 nm FinFET technology. We further incorporate channel length and temperature dependence in GCM. The generation of a full GCM model card is less than 5 min, all automated through the back propagation process. Finally, GCM is implemented in Verilog-A and passes Si2 benchmark tests, ensuring model continuity and quality in circuit simulations.
- 6 November 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 71 (1) , 254-262
Graph-Based Compact Model (GCM) for Efficient Transistor Parameter Extraction: A Machine Learning Approach on 12 nm FinFETs
Compact models for CMOS transistors usually have many fitting parameters to accurately capture the device properties, especially for the cutting-edge CMOS technology. As a result, parameter extraction of compact models requires a lot of expertise and engineering time. To overcome this barrier, we propose a new machine learning approach, graph-based compact model (GCM), to automate parameter extraction with high efficiency. GCM starts from a core set of physical equations, such as long-channel surface potential with semi-empirical analytic equations for short-channel effects. It then aggregates these physical models through graph neural networks (GNNs) to predict the final device behavior. In this approach, the analytic equations preserve physical dependencies on process and bias conditions, while the neural networks in GCM enable model training driven by a small set of measurement data. Using GCM, we demonstrate parameter extraction with high accuracy for dc and ac data from GlobalFoundries 12 nm FinFET technology. We further incorporate channel length and temperature dependence in GCM. The generation of a full GCM model card is less than 5 min, all automated through the back propagation process. Finally, GCM is implemented in Verilog-A and passes Si2 benchmark tests, ensuring model continuity and quality in circuit simulations.