Kieran Dalton
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Kieran Dalton has a total of 28 co-authors. Here are the top co-authors by number of shared publications:
- Andreas Wallraff
Department of Physics, ETH Zürich, Zürich, Switzerland
4 shared publications - Jean-Claude Besse
Department of Physics, ETH Zürich, Zürich, Switzerland
4 shared publications Mohsen Bahrami Panah
Department of Physics, ETH Zürich, Zürich, Switzerland
4 shared publicationsAlexander Flasby
Department of Physics, ETH Zürich, Zürich, Switzerland
3 shared publicationsCrispin H. W. Barnes
Cavendish Laboratory, Department of Physics, University of Cambridge, Cambridge CB3 0HE, United Kingdom
3 shared publications- Dante Colao Zanuz
ETH Zurich
3 shared publications
Latest Publications
- Top Cited PapersOpen Access
- 11 February 2026
- Published by Springer Nature in EPJ Quantum Technology
- Vol. 13 (1)
Performance characterization of a multi-module quantum processor with static inter-chip couplers
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$ , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.- 11 February 2026
- Published by Springer Nature in EPJ Quantum Technology
- Vol. 13 (1)
Top Cited PapersOpen AccessPerformance characterization of a multi-module quantum processor with static inter-chip couplers
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$ , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors. - Open Access
- 16 December 2025
- Published by American Physical Society (APS) in PRX Quantum
- Vol. 6 (4)
Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
- 16 December 2025
- Published by American Physical Society (APS) in PRX Quantum
- Vol. 6 (4)
Open AccessResource-Efficient Cross-Platform Verification with Modular Superconducting Devices
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
- Open Access
Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state -- a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two three-qubit modules on a single carrier chip, with connectivity for intra- and inter-module entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an inter-module two-qubit gate enables sub-exponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of four for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
Open AccessResource-Efficient Cross-Platform Verification with Modular Superconducting Devices
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state -- a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two three-qubit modules on a single carrier chip, with connectivity for intra- and inter-module entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an inter-module two-qubit gate enables sub-exponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of four for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
- Open Access
Performance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$, consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.Open AccessPerformance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$, consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors. - Open Access
- 12 April 2024
- Published by American Physical Society (APS) in Physical Review A
- Vol. 109 (4) , 042413
Layering and subpool exploration for adaptive variational quantum eigensolvers: Reducing circuit depth, runtime, and susceptibility to noise
Adaptive variational quantum eigensolvers (ADAPT-VQEs) are promising candidates for simulations of strongly correlated systems on near-term quantum hardware. To further improve the noise resilience of these algorithms, recent efforts have been directed towards compactifying, or layering, their Ansatz circuits. Here, we broaden the understanding of the algorithmic layering process in three ways. First, we investigate the noncommutation relations between the different elements that are used to build ADAPT-VQE Ansätze. In doing so, we develop a framework for studying and developing layering algorithms, which produce shallower circuits. Second, based on this framework, we develop a new subroutine that can reduce the number of quantum-processor calls by optimizing the selection procedure with which a variational quantum algorithm appends Ansatz elements. Third, we provide a thorough numerical investigation of the noise-resilience improvement available via layering the circuits of ADAPT-VQE algorithms. We find that layering leads to an improved noise resilience with respect to amplitude-damping and dephasing noise, which, in general, affect idling and nonidling qubits alike. With respect to depolarizing noise, which tends to affect only actively manipulated qubits, we observe no advantage of layering.
- 12 April 2024
- Published by American Physical Society (APS) in Physical Review A
- Vol. 109 (4) , 042413
Open AccessLayering and subpool exploration for adaptive variational quantum eigensolvers: Reducing circuit depth, runtime, and susceptibility to noise
Adaptive variational quantum eigensolvers (ADAPT-VQEs) are promising candidates for simulations of strongly correlated systems on near-term quantum hardware. To further improve the noise resilience of these algorithms, recent efforts have been directed towards compactifying, or layering, their Ansatz circuits. Here, we broaden the understanding of the algorithmic layering process in three ways. First, we investigate the noncommutation relations between the different elements that are used to build ADAPT-VQE Ansätze. In doing so, we develop a framework for studying and developing layering algorithms, which produce shallower circuits. Second, based on this framework, we develop a new subroutine that can reduce the number of quantum-processor calls by optimizing the selection procedure with which a variational quantum algorithm appends Ansatz elements. Third, we provide a thorough numerical investigation of the noise-resilience improvement available via layering the circuits of ADAPT-VQE algorithms. We find that layering leads to an improved noise resilience with respect to amplitude-damping and dephasing noise, which, in general, affect idling and nonidling qubits alike. With respect to depolarizing noise, which tends to affect only actively manipulated qubits, we observe no advantage of layering.
- Open Access
Quantifying the effect of gate errors on variational quantum eigensolvers for quantum chemistry
Variational quantum eigensolvers (VQEs) are leading candidates to demonstrate near-term quantum advantage. Here, we conduct density-matrix simulations of leading gate-based VQEs for a range of molecules. We numerically quantify their level of tolerable depolarizing gate-errors. We find that: (i) The best-performing VQEs require gate-error probabilities between $10^{-6}$ and $10^{-4}$ ( $10^{-4}$ and $10^{-2}$ with error mitigation) to predict, within chemical accuracy, ground-state energies of small molecules with $4-14$ orbitals. (ii) ADAPT-VQEs that construct ansatz circuits iteratively outperform fixed-circuit VQEs. (iii) ADAPT-VQEs perform better with circuits constructed from gate-efficient rather than physically-motivated elements. (iv) The maximally-allowed gate-error probability, $p_c$, for any VQE to achieve chemical accuracy decreases with the number $\ncx$ of noisy two-qubit gates as $p_c\approxprop\ncx^{-1}$. Additionally, $p_c$ decreases with system size, even with error mitigation, implying that larger molecules require even lower gate-errors. Thus, quantum advantage via gate-based VQEs is unlikely unless gate-error probabilities are decreased by orders of magnitude.Open AccessQuantifying the effect of gate errors on variational quantum eigensolvers for quantum chemistry
Variational quantum eigensolvers (VQEs) are leading candidates to demonstrate near-term quantum advantage. Here, we conduct density-matrix simulations of leading gate-based VQEs for a range of molecules. We numerically quantify their level of tolerable depolarizing gate-errors. We find that: (i) The best-performing VQEs require gate-error probabilities between $10^{-6}$ and $10^{-4}$ ( $10^{-4}$ and $10^{-2}$ with error mitigation) to predict, within chemical accuracy, ground-state energies of small molecules with $4-14$ orbitals. (ii) ADAPT-VQEs that construct ansatz circuits iteratively outperform fixed-circuit VQEs. (iii) ADAPT-VQEs perform better with circuits constructed from gate-efficient rather than physically-motivated elements. (iv) The maximally-allowed gate-error probability, $p_c$, for any VQE to achieve chemical accuracy decreases with the number $\ncx$ of noisy two-qubit gates as $p_c\approxprop\ncx^{-1}$. Additionally, $p_c$ decreases with system size, even with error mitigation, implying that larger molecules require even lower gate-errors. Thus, quantum advantage via gate-based VQEs is unlikely unless gate-error probabilities are decreased by orders of magnitude. - Open Access
- 27 January 2024
- Published by Springer Nature in npj Quantum Information
- Vol. 10 (1) , 1-11
Quantifying the effect of gate errors on variational quantum eigensolvers for quantum chemistry
Variational quantum eigensolvers (VQEs) are leading candidates to demonstrate near-term quantum advantage. Here, we conduct density-matrix simulations of leading gate-based VQEs for a range of molecules. We numerically quantify their level of tolerable depolarizing gate-errors. We find that: (i) The best-performing VQEs require gate-error probabilities between 10−6 and 10−4 (10−4 and 10−2 with error mitigation) to predict, within chemical accuracy, ground-state energies of small molecules with 4 − 14 orbitals. (ii) ADAPT-VQEs that construct ansatz circuits iteratively outperform fixed-circuit VQEs. (iii) ADAPT-VQEs perform better with circuits constructed from gate-efficient rather than physically-motivated elements. (iv) The maximally-allowed gate-error probability, pc, for any VQE to achieve chemical accuracy decreases with the number NII of noisy two-qubit gates as $${p}_{c}\mathop{\propto }\limits_{\displaystyle{ \sim }}{N}_{{{{\rm{II}}}}}^{-1}$$ . Additionally, pc decreases with system size, even with error mitigation, implying that larger molecules require even lower gate-errors. Thus, quantum advantage via gate-based VQEs is unlikely unless gate-error probabilities are decreased by orders of magnitude.- 27 January 2024
- Published by Springer Nature in npj Quantum Information
- Vol. 10 (1) , 1-11
Open AccessQuantifying the effect of gate errors on variational quantum eigensolvers for quantum chemistry
Variational quantum eigensolvers (VQEs) are leading candidates to demonstrate near-term quantum advantage. Here, we conduct density-matrix simulations of leading gate-based VQEs for a range of molecules. We numerically quantify their level of tolerable depolarizing gate-errors. We find that: (i) The best-performing VQEs require gate-error probabilities between 10−6 and 10−4 (10−4 and 10−2 with error mitigation) to predict, within chemical accuracy, ground-state energies of small molecules with 4 − 14 orbitals. (ii) ADAPT-VQEs that construct ansatz circuits iteratively outperform fixed-circuit VQEs. (iii) ADAPT-VQEs perform better with circuits constructed from gate-efficient rather than physically-motivated elements. (iv) The maximally-allowed gate-error probability, pc, for any VQE to achieve chemical accuracy decreases with the number NII of noisy two-qubit gates as $${p}_{c}\mathop{\propto }\limits_{\displaystyle{ \sim }}{N}_{{{{\rm{II}}}}}^{-1}$$ . Additionally, pc decreases with system size, even with error mitigation, implying that larger molecules require even lower gate-errors. Thus, quantum advantage via gate-based VQEs is unlikely unless gate-error probabilities are decreased by orders of magnitude.