Vladimir Cherman

Nowadays the AI\HPC devices are becoming more advanced, therefore, the demand for larger packages is rising. However, increased package sizes are causing larger warpage levels to occur. As a result of larger warpage levels, the effects of warpage on the thermal performance of Thermal Interface Materials (TIMs) inside the packages become more critical. However, current thermal characterization methodologies (e.g., ASTM D5470) use ideal surface conditions during testing and overlook the effects of chip package interactions, such as temperature and pressure dependent warpage during operation. Such conditions could deteriorate the contact or coverage of TIMs with die and the heat spreader/heat sink elements in the package. In addition, lack of fully coupled thermal and mechanical analysis of TIMs inside IC packages increases the risk of selecting improper TIMs, which might cause thermal performance issues. To address these problems, we combine in-situ thermal characterization of TIMs using packaged thermal test vehicles and fully coupled thermal and mechanical modelling of the package in realistic application conditions. Fully coupled thermal and mechanical modelling includes the assembly induced warpage, warpage induced gaps at TIM-Cold Plate interface, pressure dependent TIM coverage and their overall effects on the thermal performance of both TIM and the packaging. The results of this study show that warpage of the die can play a crucial role in the thermal performance of the package based on the mechanical properties of the thermal interface materials, bond line thickness and pressure. Using the coupled thermal and mechanical modelling, the mechanisms behind the non-uniform temperature distributions measured by packaged thermal test vehicle are explained, as the temperature difference between the center and the corner of the chip can increase up to a factor 2, caused by warpage induced gaps. Outcomes of this work can be used as a guideline for selecting proper thermal interface materials for improved thermal management of IC packaging.

This paper explores the challenges of microbump pitch scaling down to 5 μm for chiplet applications, including TCB tool alignment accuracy, fabrication process limitations, CTE mismatch, metal oxide reduction, and reliability concerns for die to wafer bonding. An approach called embedded bumps together with fluxless TCB are introduced to mitigate the challenges. Additionally, it discusses qubit, interposer and CMOS chips integration in 2.5D chiplet and 3D architectures for cold and quantum computing applications, where indium is used as the solder metal where successful bonding results for 20 μm pitch indium bumps are shown.

In this paper, we introduce a modular thermal modeling methodology, BTE-FEM, that combines the Boltzmann Transport Equation (BTE) with Finite Element Modeling (FEM) for simulations of advanced back-end-of-line (BEOL) stacks with high accuracy and efficiency. BTE-FEM is validated against direct BTE-based simulations using simplified BEOL stack test cases across various technology nodes and via connectivity configurations. It is demonstrated that conventional FEM, using bulk material properties, increasingly underestimates the BEOL thermal resistance as the technology node scales. In contrast, the BTE-FEM developed in this study demonstrates good agreement with direct BTE simulations for all test cases, but at much shorter runtimes. The impact of material properties, metal densities, and boundary conditions on the derived BEOL thermal properties are benchmarked and the developed models are experimentally validated at two distinct technology nodes. Finally, the developed methodology is applied to a 12-layer, 18 nm metal pitch BEOL stack from an A10 high density core design, demonstrating its ability to simulate complex and realistic BEOL routings with the precision of direct BTE simulations while substantially reduced simulation time. This approach enables extensive Design of Experiments (DOE) for fast turnaround design iterations.

As high-power electronics cooling for high heat fluxes above 100 W/cm ² continues to become a more and more pressing matter, work to provide an efficient and effective cooling solution in turn continues also. In the ecosystem of active liquid cooling solutions, it is the cooling performance that is provided within a given flow rate and pressure drop budget that determines efficiency. Liquid jet impingement on the bare die has been proven to provide good cooling performance that is not impeded by the thermal resistance of thermal interface materials. However, system optimizations are also necessary to provide the desired cooling performance within the restrictions of flow rate and pressure drop. A modeling study and experimental demonstrations were done in this work to showcase improvement options within restricted operating conditions. The modeling study shows that adjustment of inlet- and outlet-nozzle diameter, nozzle-to-target spacing, and nozzle pitch allows for optimizing the achieved heat transfer coefficient at given operating conditions. Based on this modeling study, a reference cooler and different improved demonstrators were built and within the same budget for coolant flow rate and driving pressure drop an improvement of effective heat transfer coefficient by 122% from 4.9 W/cm ² K to 10.4 W/cm ² K was achieved.

The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imec's proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSV's and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.

FET arrays are investigated from the viewpoint of Chip-Package Interaction (CPI) sensor suitability and presented as a possible solution for experimental characterization of CPI effects during 3D assembly steps: Stacking and packaging. The study presents a methodology consisting of an experimental approach with the support of FEM modeling. The use of the transistors as stress sensors covering in-plane stress components is justified, after which the applicability of the transistors to the actual stacking and packaging stress states is discussed. Calibration to in-plane stress of long and short channel transistors, p and n type, is performed to obtain sensor sensitivities and link stress to current shift by according calculated piezocoefficients. Testing the FET arrays as sensors is firstly done by means of a simple structure where a die is glued to a plastic substrate. The electrical measurements are compared to FEM models and profilometric scans. The sensors are next utilized to obtain first results from 3D stacking and packaging. The underfill - microbump mechanism in a 2-die stack is quantified and initial results on overmould impact are discussed.

Besides the stress around Cu TSV's, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

3D-IC stacking is a promising technique for miniaturization and performance enhancement of electronic systems. The complexity of the interconnect structures, combined with the reduced thermal spreading in the thinned dies used for the stacking and the poorly thermally conductive adhesives adopted for bonding the dies in the stack complicate the modeling of the thermal behavior of 3D ICs. The same amount of energy dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die with respect to a single die. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, the impact of TSVs and the Cu-Cu bonding on the temperature profile of the top and bottom die of a 3D stack is characterized by using dedicated test chips with integrated thermal heaters and temperature sensors. A specific experimental set-up is conceived and used to evaluate and improve the thermal models for the 3D stacks.