Takaya Uchino

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

Sub-terahertz (Sub-THz) communication systems are a promising technology for next-generation high-speed, high-capacity wireless networks. Achieving this requires highly integrated antenna-in-package (AiP) solutions combining antennas and radio frequency integrated circuits (RFICs). However, high-frequency operation and dense integration increase RFIC heat density, potentially degrading AiP performance and reliability. This article proposes a sub-THz AiP with both excellent RF and thermal performance. The design features a multilayer antenna structure on a low-loss dielectric substrate, minimizing RFIC-to-antenna connections and radiating toward the substrate edge. A dual-sided heat dissipation structure is also introduced for efficient thermal management in stacked configurations. Validation through simulations and measurements confirmed good reflection characteristics ( $\vert $ S $11\vert \lt $ –10 dB), 15 dBi gain, and thermal resistance below 4.1 K/W. 2-D beam steering was also demonstrated, highlighting the effectiveness of the proposed co-design approach.

This article introduces a compact D-band phase shifter, which achieves high-resolution phase steps and ultra-low phase error, designed for the sixth-generation (6G) mobile network. The proposed design integrates two novel circuit architectures: a feedback fine-tuning phase shifter (FFPS) provides precise phase control with fine 0.1° steps over a 22.5° range by using a feedback transmission line (TL) to enhance gain and tuning range. The second architecture is a two-mode non-uniform propagation delay phase shifter (2-mode NU-PDPS), which enables coarse phase tuning with 22.5° steps, covering a full 360° phase range. It employs non-uniform MOSFET sizing to realize ideal TL operation. In addition, two modes are introduced in the quarter-wave TL to increase phase resolution without increasing area and thus achieves a core area of 0.06 $\text {mm}^{2}$ . The proposed phase shifter operates with 0.1° steps over a 360° fine-tuning range within the frequency range of 150–160 GHz. It achieves an rms phase error of 0.68°, the lowest among reported phase shifters in this frequency range. The total power consumption is 5mW at 1.0-V VDD, with an insertion loss of −2.5dB.