Humiao Li

Multi-level-cell (MLC) resistive random-access memory (RRAM) promises superior computational density and energy efficiency for compute-in-memory (CIM) systems, yet its potential is limited by analog RRAM instability and the power-hungry bitline (BL) regulation amplifiers in prior Ohm’s-law-based designs. We demonstrate a 180-nm CIM macro with process-optimized back-end-of-line (BEOL) HfO₂ MLC RRAM. The devices exhibit stable 3-bit conductance states (74%. Silicon measurements of the 180-nm prototype deliver a peak energy (area) efficiency of 819 TOPS/W/bit (1.115 TOPS/mm²/bit). Furthermore, post-layout simulations of a 22-nm implementation project 14,123 TOPS/W/bit and 412.2 TOPS/mm²/bit, respectively.

Logic-in-Memory (LiM) architecture uses its unique tunable memory states to realize different logic functions within a single cell, greatly improving its area efficiency. In this work, we propose a reconfigurable complementary oxide-based 1FeFET-1pFET (1F1P) LiM cell that supports 14 types of reconfigurable logic operations. Leveraging the complementary characteristics of FeFET and pFET devices, the proposed design achieves a low static power consumption down to 10.97 pW. Array-level Spectre simulation based on the 1F1P structure shows an energy efficiency of 74 TOPS/W for the INT4 MAC in ResNet-20 inference on the CIFAR-10 dataset with peak throughput of 671 GOPS, underscoring the potential of complementary 1F1P for next-generation low-power reconfigurable logic.

This brief presents a novel compute-SRAM bitcell design capable of performing 1-bit digital multiplication for digital compute-in-memory (DCIM) macros. Unlike the conventional approach, which requires 10 transistors (6T SRAM + 4T NOR), the proposed bitcell achieves the same functionality with only 8 transistors. This is accomplished by efficiently embedding a NOR gate into the latch pair of the traditional 6T bitcell through the addition of two transistors. The design enables efficient in-bitcell compute operations, achieving a 37.5% reduction in area and a 41.5% reduction in leakage compared to the 10T counterpart. Moreover, the proposed bitcell maintains robust stability in terms of write and hold static noise margins, thanks to the sizing strategy and gate overdrive. To validate the design, a 64× 64 DCIM macro was fabricated using a 22nm CMOS process. The macro demonstrates a peak energy efficiency of 126 TOPS/W at INT4 precision under a 0.55 V supply.