Zhichao Cheng
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Zhichao Cheng has a total of 6 co-authors. Here are the top co-authors by number of shared publications:
- Feng He
Beijing Huairou Laboratory, Beijing 101409, China
1 shared publication - Ling Sang
Beijing Institute of Smart Energy, Beijing 102209, China
1 shared publication - Peng Cui
Institute of Novel Semiconductors, Shandong University 2 , Jinan 250100
1 shared publication - Rui Jin
Beijing Huairou Laboratory, Beijing 101409, China
1 shared publication - Yawei He
Beijing Huairou Laboratory, Beijing 101409, China
1 shared publication - Zheyang Li
State Key Laboratory of Advanced Power Transmission Technology, Beijing Institute of Smart Energy, Beijing 102209, China
1 shared publication
Latest Publications
- Open Access
- 19 June 2026
- Published by MDPI AG in Electronics
- Vol. 15 (12) , 2721
Investigation on Degradation of Switching Characteristics in SiC MOSFETs Under Repetitive Surge Current
Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (td(on)), rise time (tr), and turn-on loss (EON) show no significant changes. In contrast, the turn-off delay time (td(off)), fall time (tf), and turn-off loss (EOFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (VTH) and the increase in gate-source capacitance (CGS) and gate-drain capacitance (CGD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance.
- 19 June 2026
- Published by MDPI AG in Electronics
- Vol. 15 (12) , 2721
Open AccessInvestigation on Degradation of Switching Characteristics in SiC MOSFETs Under Repetitive Surge Current
Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (td(on)), rise time (tr), and turn-on loss (EON) show no significant changes. In contrast, the turn-off delay time (td(off)), fall time (tf), and turn-off loss (EOFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (VTH) and the increase in gate-source capacitance (CGS) and gate-drain capacitance (CGD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance.