0.193 pJ/bit and 0.02 pJ/bit/dB Reference-Voltage-Less Die-to-Die Interface With State-Dependent Differentiator-TIA-Integrated RX
- 1 November 2026
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 73 (11) , 7331-7342
Abstract
No abstract availableFunding Information
- Samsung Research Funding and Incubation Center of Samsung Electronics (SRFC-IT2401-06)
- National Research Foundation of Korea
- Korean Government [Ministry of Science and ICT (MSIT)] (RS-2024-00334247)
This publication has 22 references indexed in Scilit:
- A 118.89 Tb/s/mm/pJbit 18-Gb/s/wire Run-LengthTolerant Transition-Driven AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces2025
- A 4-24 Gb/s/wire Single-Ended NRZ Die-to-Die Transceiver with Low Latency for UCle Standard Package in 4nm FinFET2025
- A 23.5-fJ/b/dB 15.2-Gb/s/pin Switched-Capacitor-Driven On-Chip Link with Half-VDD DC Biasing and ISI Mitigation2025
- A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation2025
- 22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces2025
- A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging2025
- An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM InterfacesIEEE Access, 2024
- A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces2022
- 6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels2020
- A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die CommunicationIEEE Journal of Solid-State Circuits, 2016