Joo-Hyung Chae

Although probabilistic computing offers a route to quantum‐inspired optimization at room temperature, existing probabilistic bits (p‐bits) often depend on non‐CMOS devices or circuit‐intensive randomness. Here, we report a CMOS‐compatible p‐bit that harnesses intrinsic random telegraph noise (RTN) in a fully depleted silicon‐on‐insulator field‐effect transistor to produce stochastic binary outputs with direct gate‐voltage control. The capture and emission dynamics follow Shockley–Read–Hall (SRH) kinetics, yielding a quantitative sigmoid bias‐to‐probability transfer, and the dwell‐time statistics exhibit Poisson behavior consistent with memoryless switching. Pairwise statistical independence between independently measured RTN streams is supported through probabilistic Boolean operations and cross‐correlation analysis. Using the experimentally derived RTN probability response, we perform an RTN‐derived numerical emulation of simulated annealing for the two‐dimensional hydrophobic–polar protein‐folding benchmark, reaching low‐energy configurations with fewer stochastic update iterations than the number of candidate conformations evaluated by exhaustive enumeration. We further map the same update pipeline into a digital logic design using integer energy evaluation and lookup‐table probability mapping, providing a practical pathway toward CMOS‐based probabilistic accelerators. Collectively, these results elevate intrinsic transistor noise from an unwanted artifact to a gate‐tunable, CMOS‐compatible stochastic primitive, providing a physically grounded pathway toward CMOS‐based probabilistic processors.

A single-ended transmitter (TX) employing a charge-pump-aided main and sub pre-emphasis feed-forward equalizer (FFE) for low-power memory interfaces is presented. By overcoming the voltage headroom limitation of V_SS termination, the proposed scheme increases the voltage swing while compensating for channel loss. To mitigate FFE degradation at high data rates and under severe channel loss, an additional on-demand sub pull-up FFE driver and sub pull-down charge pump are introduced. These selectively enhance equalization during bit-toggling patterns and at transitions after consecutive identical digits, improving signal integrity compared with conventional designs. Fabricated in a 28-nm CMOS process, the TX occupies an active area of 0.0065 mm² and achieves 18-Gb/s single-ended signal transmission over a channel with a –15.7 dB loss. The measured power consumption is 18.85 mW, corresponding to 1.05 pJ/bit and a figure of merit of 0.067 pJ/bit/dB.

This paper presents a 28-nm CMOS low-noise amplifier (LNA) designed for cryogenic quantum computing systems. The proposed three-stage common-source LNA employs a pole-aligning technique to achieve an ultra-flat and wideband gain, while maintaining robustness against temperature-dependent metal conductivity variation thanks to removing ground planes beneath the inductors. Measurement results at 4 K demonstrate a 30.4 dB gain, 6.1 GHz 1-dB bandwidth (4.2 GHz - 10.3 GHz), 0.36 dB average noise figure, and 4.8 mW power consumption, showing excellent stability and bandwidth performance compared with prior cryogenic LNAs.