FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
Authors:
- Reza Rezaeian FarashahiRFReza Rezaeian Farashahi
- Bahram RashidiBRBahram Rashidi
- Sayed Masoud SayediSSSayed Masoud Sayedi
- 1 August 2014
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 45 (8) , 1014-1025
Abstract
No abstract availableThis publication has 39 references indexed in Scilit:
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