Oxide-Based CMOS Logic Circuits Enabled by Monolithically 3D Stacked SnO x p-FET and IGZO n-FET With Matched Threshold Voltage

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Abstract
Low-temperature processable oxide-based devices provide a promising avenue to monolithic 3D (M3D) IC chips. Here, oxide-based complementary metal-oxide-semiconductor (CMOS) logic circuits consisting of M3D stacked field effect transistors (FETs) – SnO ${}_{\mathbf {x}}$ p-FET at the bottom and IGZO n-FET at the top are reported. By controlling the deposition process and keeping the entire fabrication thermal budget below $250~^{\circ }$ C suitable for BEOL integration process, excellent uniformity and matched threshold voltage ( ${V} _{\mathbf {th}}$ ) of 0.5 V are achieved for both types of devices. As a result, minimally skewed operation of the stacked inverter is ensued, with voltage gain reaching a decently high value of 100.6 V/V at a V ${}_{\mathbf {DD}}$ of 1.5 V. Key logic gates utilizing the M3D stacked FETs including NAND, NOR, and SRAM cell were first demonstrated (SnO ${}_{\mathbf {x}}$ p-FET based), showing robust and reliable logical functionality, together with a three-stage ring oscillator achieving a ringing frequency up to 62.5 kHz at a ${V} _{\mathbf {DD}}$ of 2.5 V.
Funding Information
  • National Key Research and Development Project of China (2023YFB2806300)
  • National Natural Science Foundation of China (W2532048)
  • National Natural Science Foundation of China (62174074)
  • National Natural Science Foundation of China (62104091)
  • National Natural Science Foundation of China (52273246)
  • Shenzhen Municipal Fundamental Research Program (JCYJ20220530115014032)
  • Shenzhen Municipal Fundamental Research Program (JCYJ20220530115204009)
  • Zhujiang Young Talent Program (2021QN02X362)
  • Guangdong Provincial Department of Education Innovation Team Program (2021KCXTD012)
  • School of Microelectronics - CIMCube Technology (SME-CIMCube) Joint Laboratory and Guangdong Provincial Engineering Research Center of 3-D Integration

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