Jiqing Lu

Logic-in-Memory (LiM) architecture uses its unique tunable memory states to realize different logic functions within a single cell, greatly improving its area efficiency. In this work, we propose a reconfigurable complementary oxide-based 1FeFET-1pFET (1F1P) LiM cell that supports 14 types of reconfigurable logic operations. Leveraging the complementary characteristics of FeFET and pFET devices, the proposed design achieves a low static power consumption down to 10.97 pW. Array-level Spectre simulation based on the 1F1P structure shows an energy efficiency of 74 TOPS/W for the INT4 MAC in ResNet-20 inference on the CIFAR-10 dataset with peak throughput of 671 GOPS, underscoring the potential of complementary 1F1P for next-generation low-power reconfigurable logic.

Low-temperature processable oxide-based devices provide a promising avenue to monolithic 3D (M3D) IC chips. Here, oxide-based complementary metal-oxide-semiconductor (CMOS) logic circuits consisting of M3D stacked field effect transistors (FETs) – SnO ${}_{\mathbf {x}}$ p-FET at the bottom and IGZO n-FET at the top are reported. By controlling the deposition process and keeping the entire fabrication thermal budget below $250~^{\circ }$ C suitable for BEOL integration process, excellent uniformity and matched threshold voltage ( ${V} _{\mathbf {th}}$ ) of 0.5 V are achieved for both types of devices. As a result, minimally skewed operation of the stacked inverter is ensued, with voltage gain reaching a decently high value of 100.6 V/V at a V ${}_{\mathbf {DD}}$ of 1.5 V. Key logic gates utilizing the M3D stacked FETs including NAND, NOR, and SRAM cell were first demonstrated (SnO ${}_{\mathbf {x}}$ p-FET based), showing robust and reliable logical functionality, together with a three-stage ring oscillator achieving a ringing frequency up to 62.5 kHz at a ${V} _{\mathbf {DD}}$ of 2.5 V.

The lack of low temperature processable, high-performance p-type oxide thin-film transistors (TFTs) limits their implementation in monolithically integrated back-end-of-line (BEOL) CMOS circuitries. In this work, we demonstrate a reactive magnetron-sputtered SnO_x TFT with unprecedented hole field-effect mobility (μ_FE-hole) of 38.7 cm²/V·s, as well as an on/off current ratio (I_on/off) of 2.5 × 10³ and lower subthreshold swing (SS) of 240.9 mV/dec when compared to reported works on p-type oxide-based TFTs. Material characterization correlated with the SnO_x TFTs' electrical behavior elucidated the performance to the structural and compositional phase modulation of the SnO_x thin films, modulated by O₂ partial pressure during deposition and post-encapsulation annealing. By integrating the SnO_x TFT with an IGZO TFT in both planar and stacked complementary FET-like form, we demonstrated a true oxide-based CMOS inverter, achieving one of the highest voltage gains of 57 and the lowest static power consumption down to 34 pW for both on and off states.

In this work, the effect of Ar plasma at the S/D contact in a low temperature (200°) fabricated ALD ZnO thin-film transistors (TFTs) for contact resistance reduction is systematically studied. With an optimized Ar plasma process time, the contact resistance is significantly reduced by >50% from 170 to $84 {\sf \Omega }/\mu \text{m}$ . This reduction is attributed to the oxygen vacancies modulating the effective contact barrier height, as elucidated by detailed AFM and XPS analysis. Consequently, the effective field-effect mobility ( $\mu _{\textit {FE}}$ ) of the TFT is increased by 50% to 39.2 cm ² /Vs. The $\mu _{\textit {FE}}$ of the developed TFT is one of the highest reported thus far using ALD process at the lowest temperature. The advances achieved in this work provide valuable insight into the defect’s regulation mechanism of ZnO-metal contact and its effect on the TFTs performance. This approach paves a pathway to further develop ZnO TFTs in applications in high-speed computational circuitries.