A simple and high performance charge pump based on the self-cascode transistor

This publication has 29 references indexed in Scilit:

• Source‐switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL
  Electronics Letters, 2016
• A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs
  Microelectronics Journal, 2015
• A 1 V CMOS programmable accurate charge pump with wide output voltage range
  Microelectronics Journal, 2011
• Low-glitch, high-speed charge-pump circuit for spur minimisation
  Electronics Letters, 2009
• A buffered charge pump with zero charge sharing
  2008
• A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump
  IEEE Transactions on Circuits and Systems II: Express Briefs, 2007
• Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies
  IEEE Journal of Solid-State Circuits, 2006
• A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability
  IEEE Journal of Solid-State Circuits, 1999
• A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation
  IEEE Journal of Solid-State Circuits, 1996
• A variable delay line PLL for CPU-coprocessor synchronization
  IEEE Journal of Solid-State Circuits, 1988