Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler
Open Access
- 12 March 2024
- journal article
- research article
- Published by Wiley in International Journal of RF and Microwave Computer-Aided Engineering
- Vol. 2024, 1-7
Abstract
This paper presents the design and measurements of a 215-252GHz 40nm bulk CMOS frequency doubler with a 6.8dBm deliverable peak output power and a conversion gain of 11.8dB. The designed chip is composed of a 28.5dB gain 6-stages 110GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795mm2 and shows a total DC power dissipation of 262mW and DC-RF efficiency of 1.87.Keywords
Funding Information
- Ministry of Internal Affairs and Communications (JPJ000254)
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