Issei Watanabe

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

Sub-terahertz (Sub-THz) communication systems are a promising technology for next-generation high-speed, high-capacity wireless networks. Achieving this requires highly integrated antenna-in-package (AiP) solutions combining antennas and radio frequency integrated circuits (RFICs). However, high-frequency operation and dense integration increase RFIC heat density, potentially degrading AiP performance and reliability. This article proposes a sub-THz AiP with both excellent RF and thermal performance. The design features a multilayer antenna structure on a low-loss dielectric substrate, minimizing RFIC-to-antenna connections and radiating toward the substrate edge. A dual-sided heat dissipation structure is also introduced for efficient thermal management in stacked configurations. Validation through simulations and measurements confirmed good reflection characteristics ( $\vert $ S $11\vert \lt $ –10 dB), 15 dBi gain, and thermal resistance below 4.1 K/W. 2-D beam steering was also demonstrated, highlighting the effectiveness of the proposed co-design approach.

To realize the practical application of sub-THz band wireless communication toward 6G, it is necessary to develop AiP modules with compact size and low cost. This letter discusses the design of a miniaturized AiP module for high-speed wireless communication targeting extended reality (XR) applications in medical operating rooms as an example of 6G use cases. By integrating waveguide antenna array along with a compact divider/combiner within the multilayer substrates, the module achieves a small form factor of $8.42\times 20.0\times 1.37$ mm while integrating radio frequency integrated circuit (RFIC) and peripheral surface mount components. The measurement shows a data rate of 40 Gb/s at a 3 m distance in the 150 GHz band with an excellent transmission energy efficiency of 35.7 pJ/bit.

A new film material, MW300, that is both compatible with build-up processes and capable of maintaining low dielectric loss, has been developed. Measurements of the dielectric properties of MW300 in the subterahertz band exhibited a loss tangent, tan δ of 0.0022 at 160 GHz, demonstrating lower loss compared to conventional build-up compatible organic materials. Analysis of the transmission loss in microstrip lines (MSLs) indicated that dielectric loss is more dominant than conductor loss in the subterahertz region, suggesting that using low-dielectric-loss materials is effective in reducing transmission loss. MSLs were fabricated on build-up substrates using both conventional materials and MW300. Measurements of the transmission loss confirmed the analytical predictions. The MSL using MW300 achieved a low-loss measurement result of 0.10 dB/mm in the 160-GHz band.

This paper presents the design and measurements of a 215-252GHz 40nm bulk CMOS frequency doubler with a 6.8dBm deliverable peak output power and a conversion gain of 11.8dB. The designed chip is composed of a 28.5dB gain 6-stages 110GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795mm² and shows a total DC power dissipation of 262mW and DC-RF efficiency of 1.87.

We investigated the growth mechanism and crystallographic structures of GaSb dots as a nucleation layer and GaSb thin films grown on a Si(001) substrate by molecular beam epitaxy using atomic force microscopy and transmission electron microscopy (TEM). The surface morphology of the 100-nm-thick GaSb with GaSb dots drastically changed from that without them. As the GaSb dots gradually grew in size, the coalescence between the adjacent dots was repeated and the space between them was filled, thereby changing the growth mode of GaSb to two-dimensional growth and forming domain structures with terrace surfaces. The high-resolution TEM images and fast Fourier transform patterns revealed that the lattice-mismatched strain in the epitaxial GaSb thin film was almost completely relieved. Because some adatoms were rotated by 60° on the {111} facets and formed a monolayer with a wurtzite structure as a stacking fault in the initial growth stage, twinned GaSb with an inclination of 54.7° from the (001) plane was formed in addition to epitaxial GaSb. The lattice-mismatched strain was nearly relieved in the vicinity of the GaSb/Si interface because of the multiple periodic 90° and 60° misfit dislocation arrays. The formation of GaSb dots, which acted as crystal nuclei and induced periodic misfit dislocation arrays, was useful for the epitaxial growth of GaSb thin films on a Si(001) substrate—a result that will be advantageous for growing high-quality GaSb thin films, with flatter and fewer crystal defects, on a Si(001) substrate in future.

Graphene is promising for next-generation devices. However, one of the primary challenges in realizing these devices is the scalable growth of high-quality few-layer graphene (FLG) on device-type wafers; it is difficult to do so while balancing both quality and affordability. High-quality graphene is grown on expensive SiC bulk crystals, while graphene on SiC thin films grown on Si substrates (GOS) exhibits low quality but affordable cost. We propose a new method for the growth of high-quality FLG on a new template named “hybrid SiC”. The hybrid SiC is produced by bonding a SiC bulk crystal with an affordable device-type wafer and subsequently peeling off the SiC bulk crystal to obtain a single-crystalline SiC thin film on the wafer. The quality of FLG on this hybrid SiC is comparable to that of FLG on SiC bulk crystals and much higher than of GOS. FLG on the hybrid SiC exhibited high carrier mobilities, comparable to those on SiC bulk crystals, as anticipated from the linear band dispersions. Transistors using FLG on the hybrid SiC showed the potential to operate in terahertz frequencies. The proposed method is suited for growing high-quality FLG on desired substrates with the aim of realizing graphene-based high-speed devices.

To improve wireless communications systems, it is desirable to seamlessly combine fiber-based optical and terahertz wireless communications systems. In this paper, we demonstrate a waveguide optically driven terahertz wave modulator using a ring-shaped microstripline with a GaInAs photoconductive mesa structure. In this device, terahertz wave modulation is performed by controlling the photo-generated carriers in the GaInAs mesa. As a result, a maximum extinction ratio of 16.8 dB in the terahertz band was obtained with a light irradiation of 15 dBm (32 mW), and the 3 dB modulation bandwidth was approximately 170 MHz.

We report on high-frequency performance and temperature stability of zero-bias GaAsSb/InAlAs/InGaAs tunnel diodes for millimeter-wave detection in 220-330-GHz band. The average voltage sensitivity of 1400 V/W has been achieved in 0.8 × 0.8μm ² mesa devices at room temperature. Measured current-voltage characteristics revealed a superior temperature stability of the devices compared with Schottky barrier diodes. The expected sensitivity variations over a temperature range from T=17-300 K are 1.7 dB.

We fabricated a 35-nm-gate In_0.7Ga_0.3As/In_0.52Al_0.48As high electron mobility transistor by using a simple, self-aligned one-step-recessed gate procedure. An extrinsic maximum transconductance (g_{m_max}) of 1.7 S/mm and a current gain cutoff frequency (f_T) of 520 GHz were achieved at room temperature. This significantly high f_T was obtained by reducing the gate length to 35 nm and using an epitaxial structure with a 3-nm-thick InAlAs spacer layer, a 6-nm-thick InAlAs Schottky barrier layer and a 2-nm-thick InP etching stopper layer to decrease the gate-to-channel distance to 8 nm, and form simultaneously 50-nm-long side-recess structures and T-shaped gates stacked on the InAlAs Schottky barrier layer. These results are the first experimental achievement of f_T as high as 520 GHz by using the one-step-recessed gate procedure.