Within-die delay variability in 90nm FPGAs and beyond
Authors:
- Pete SedcolePSPete Sedcole
- Peter Y. K. CheungPCPeter Y. K. Cheung
- 1 December 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 97-104
Abstract
Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This paper describes accurate measurement techniques for characterising both systematic and stochastic delay variability in FPGAs. Results and analysis are presented from measurements made on a sample of 90nm devices, showing that delay per logic element varies stochastically by plusmn3.54% on average over the set. The delay also varies by up to 3.66% across a single die from correlated sources of variability. The results are extrapolated to determine the impact at future technology nodes. The predicted significant performance degradation that variability will cause demonstrates the importance of new circuit or system design techniques to cope with variations in future FPGAsKeywords
This publication has 14 references indexed in Scilit:
- Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices2006
- Death, taxes and failing chips2004
- Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices2003
- Delay defect characteristics and testing strategiesIEEE Design & Test of Computers, 2003
- Design sensitivities to variability: extrapolations and assessments in nanometer VLSI2003
- Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughnessIEEE Transactions on Electron Devices, 2003
- BIST-based delay path testing in FPGA architectures2002
- Delay variability: sources, impacts and trends2002
- Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integrationIEEE Journal of Solid-State Circuits, 2002
- Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variationsIEEE Transactions on Electron Devices, 2002