Mattias Ekström

This work describes the fabrication and characterization of a novel lateral 4H-SiC PiN diode featuring inter-device isolation technology for power integrated circuits (ICs). The device’s architecture includes thick SiO₂ blocking layers and inter-device trench isolation structures, enabling effective electrical isolation between power devices and control circuitry on a single chip. The devices demonstrate good isolation performance, with inter-device leakage currents below 5 nA at a reverse bias of 200 V. The diodes keep reverse leakage current low (<1 μA at 20 V), but exhibit non-distinct turn-on behavior. This is mostly due to the too-shallow N+ and P+ ion implantation region and high series resistance. A monolithically integrated bridge circuit operating at 50 Hz and 200 Hz validates the integration approach; however, large forward voltage drops show that the high series resistance at the device level affects overall conversion efficiency. The transfer length method (TLM) characterization reveals high sheet and contact resistances, which are responsible for the conduction limitations in the PiN diode forward performance. This study establishes the foundation for a lateral SiC device technology with promising inter-device isolation capabilities, as well as the bridge circuit built based on the lateral PiN diodes, which shows the potential of this technology for future monolithic power IC applications.

With its excellent thermal conductivity, high critical breakdown field strength, and high temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart power-integrated circuits (ICs). This work describes the design and fabrication process of a novel SiC high-voltage lateral PiN (HVLPN) diode with the addition of a lateral isolation structure with a thickness of 10 μm to achieve sufficient isolation between breakdown voltages and devices, as well as a solution for the deep etching of the SiC over 10 μm with a thick enough Hard Mask (HDM), which is required for the actual fabrication process.

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects, defects at the SiO₂/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

This chapter presents a short introduction into the physics necessary to understand the spintronic effects, like the magnetoresistance effect, spin-transfer torque, spin Hall effect, and the magnetoelectric effect. It focuses on and examines concepts and devices that are complementary metal oxide semiconductor (CMOS) compatible and present possibilities for different levels of integration into CMOS technology. The access transistor is a four terminal such as gate, source, drain, and body device for a bulk CMOS process and a three terminal device for a silicon on insulator process. The nonvolatile flip flop exploits spin-transfer torques and magnetic exchange coupling within its free layer to perform the actual computation instead of relying on external CMOS transistors. The communication between the memory and the logic is significantly decreased and the auxiliary CMOS circuits for the signal conversion between the CMOS and the spintronic domain become redundant, which in turn greatly improves the omnipresent leakage power and interconnection delay problems.

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10^-4 Ω cm²) to epitaxially grown p-type (>5×10¹⁸ cm^-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni₂Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10⁻⁶ Ω·cm² is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.