Salvador Mir

This work proposes the use of machine learning-based techniques for enhanced testability and performance calibration of an industrial 79-GHz power amplifier (PA) designed for an automotive radar system. The proposed techniques are based on a set of built-in test structures including nonintrusive process monitors based on digital ring oscillators and a built-in reflectometer. The indirect signatures provided by these test structures allow us to do the following: 1) identify defective instances of the PA under test; 2) evaluate the quality of the output matching adaptation; and 3) calibrate the performance of the PA to compensate for process variations. Defect detection is based on a defect filtering algorithm that employs outlier identification techniques; mismatch evaluation employs a machine learning regressor; and, finally, the proposed performance calibration is based on a one-shot statistical calibration that predicts the optimum configuration of the PA. The proposed techniques are experimentally demonstrated on a set of 32 fabricated chips designed in 28 nm CMOS technology.

State-of-the-art nanometric fabrication processes enable the integration of monolithic millimeter-wave (mm-wave) circuits. However, nanometric technologies are prone to process variations that may significantly impact the performance of the fabricated mm-wave circuits and dramatically reduce the fabrication yield. In order to improve the fabrication yield, extensive resources are required for tuning the functionality of each fabricated die in the production line, especially in the mm-wave domain. In this work, we implement and experimentally validate a machine learning-based calibration strategy for mm-wave circuits that significantly simplifies this tuning process. A machine learning algorithm is employed to predict the optimum values of a set of on-chip tuning knobs based on nonintrusive measurements provided by embedded process monitor circuits. The proposed technique is demonstrated on a 69-GHz power amplifier (PA) with one-shot calibration capabilities integrated in STMicroelectronics 55-nm CMOS technology. The experimental results on a set of 39 fabricated samples demonstrate the feasibility and performance of the proposed machine learning-based calibration for yield recovery and performance recentering applications.

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In this article, we leverage the power of machine learning algorithms to propose a test methodology for millimeter-wave (mm-wave) integrated circuits. The proposed test strategy is based on identifying the main process degradation mechanisms in a particular device under test (DUT) and then designing dedicated process monitor circuits to characterize this degradation and infer the DUT performance. The resulting process monitors do not load or couple to any of the DUT nodes, and the methodology can be adapted to any mm-wave device without complex codesign. The proposed test methodology is illustrated on a set of 21 fabricated samples of a 65-GHz PA designed in STMicroelectronics 55-nm CMOS technology.

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as Test Escapes (TE) and Yield Loss (YL). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme Value Theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of a RF LNA BIT technique using a bivariate model.

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.