Arnout Beckers

The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.

Fully conductive band tails cause the subthreshold swing to saturate at temperatures above 1 K. However, recent measurements indicate that below 1 K, the subthreshold swing in certain MOSFET structures resumes a linear scaling with temperature. Following this ultra-steep behavior, a new type of plateau has been measured below 1 K. In this letter, we show that hybrid band tails, with both traps and mobile states, explain this new plateau. Furthermore, hybrid band tails explain various non-saturating behaviors above 1 K. Remarkably, for entirely non-conductive band tails, the simulations and theory predict a third type of plateau below 10 mK. We hypothesize that this represents the lower bound of subthreshold swing at sub-Kelvin temperatures, which is a testable prediction from the theory.

The realization of practical, large-scale quantum computers requires the optimization of classical electronics for cryogenic operation to solve the interconnect bottleneck between quantum processors and control electronics. Devices from Fully-depleted Silicon-on-insulator (FDSOI) technology nodes are ideal for cryogenic operation due to the possibility of tuning the threshold voltage through the back-gate and reducing power consumption. However, they must be assessed in terms of not just their performance but also their reliability at conditions of interest. In this study, we present the Bias Temperature Instability (BTI) characteristics of commercial 22 nm FDSOI transistors optimized for low-power applications at temperatures ranging from 300 K down to 4 K, focusing on the impact of stress time and gate overdrive voltage. We observe that BTI remains active in both pMOS and nMOS at 4K with weak dependencies on stress magnitude and duration. Crucially, recovery from threshold voltage shifts is also slowed down at cryogenic temperatures.

While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium-gallium-zinc-oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include the following: (1) at room temperature (300 K), the devices exhibit a SS of 61 mV/dec and a low interface trap density of <1011 cm−2. (2) A SS saturation around 40 mV/dec is observed between 200 and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 17 meV. (3) At deep cryogenic temperatures, the SS increases significantly, exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id − Vg simulations based on the variable range hopping model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence bands. In this article, we present a generalization of the Boltzmann relations accounting for exponential band tails. To this end, the required Fermi-Dirac integral is first recast as a Gauss hypergeometric function, followed by a suitable transformation of that special function, and a zeroth-order series expansion using the hypergeometric series. This results in simple relations for the electron and hole densities that each involve two exponentials. One exponential depends on the temperature and the other one on the band-tail parameter. The proposed relations tend to the Boltzmann relations if the band-tail parameters tend to zero. This work comes timely for the modeling of classical semiconductor devices at cryogenic temperatures for large-scale quantum computing.

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the current in weak and moderate inversion at a given gate voltage compared to the drift-diffusion current. This phenomenon is explained by introducing a Gaussian distribution of localized states centered around the band edge. The localized states are attributed to disorder and interface traps. The proposed model allows to extract the density of localized states at the interface from the dc current measurements.

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in bench-marking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2K

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ${T}$ ), referred to as “excess 1/f noise,” observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence bands. In this article, we present a generalization of the Boltzmann relations accounting for exponential band tails. To this end, the required Fermi–Dirac integral is first recast as a Gauss hypergeometric function followed by a suitable transformation of that special function and a zeroth-order series expansion using the hypergeometric series. This results in simple relations for the electron and hole densities that each involve two exponentials. One exponential depends on the temperature and the other one on the band-tail parameter. The proposed relations tend to the Boltzmann relations if the band-tail parameters tend to zero. This work is timely for the modeling of semiconductor devices at cryogenic temperatures for large-scale quantum computing.