Sen Yin

In recent years, electronic design automation methodologies based on hierarchical multilevel bottom-up (BU) design approaches are emerging and successfully applied for RF system design. In this article, we propose a design automation methodology for the synthesis of millimeter-wave (mm-wave) systems via BU approaches, including sizing and layout generation. First, uniformly sampled passive and active component libraries with prepared layouts and S-parameter files are constructed during the offline preparation stage. Second, the BU sizing from the device level to the system level has been demonstrated via multiobjective optimization algorithms, while an improved Euclidean mapping strategy is proposed to efficiently search over circuit-level Pareto-optimal fronts (POFs) in the system-level optimization. Third, the parameterized DRC/LVS clean layout can be hierarchically generated for the system-level POFs. Compared to flat optimization at the system level, the proposed method greatly reduces the size of the search space with the highest accuracy possible and can be used for the synthesis of complex mm-wave systems. The proposed method achieves a $10\times $ runtime speedup in the system-level optimization with better optimization results.

This article presents a datasheet-driven empirical model of silicon carbide (SiC) MOSFET, in which both the static $\textit{I}$ – $\textit{V}$ and dynamic $\textit{C}$ – $\textit{V}$ characteristics are accurately captured by using nonsegmented empirical equations. Compared with the existing models, this model features on describing the first quadrant conduction $\textit{I}$ – $\textit{V}$ characteristics through nonsegmented empirical equations while considering the intrinsic physical mechanisms, which is beneficial for improving the convergence capability. Moreover, the nonlinear Miller capacitance $\textit{C}_{\text{gd}}$ is accurately captured considering the shielding effect caused by the adjacent p-wells. Apart from the abovementioned added features, a parameter extraction procedure is also proposed, in which all the parameter values could be directly extracted from the data provided in the commercial datasheet. The accuracy of the proposed model is verified through the comparisons between the modeling results and experimental data from the datasheet. Furthermore, the convergence capability of the proposed model is verified by simulating a seven-level cascaded H-bridge (CHB) inverter, in which 12 devices are included. The experimental double pulse test is finally carried out to verify the feasibility of the proposed model in simulating the dynamic transients.

This letter presents an ultra-compact bi-directional $Ka$ -band front-end module (FEM) in 65-nm CMOS technology. In this design, the receiver (RX) path is stacked into the transmitter (TX) path by using a magnetic self-canceling technique, improving area efficiency greatly with negligible performance penalty. Furthermore, a three-inductor coupled resonator is elaborately designed to realize the functions of the balun and input–output matching network (MN) of the RX/TX simultaneously. The measurement results demonstrate that the proposed FEM achieves 18.2-dB peak gain with a 3.8-dB minimum noise figure (NF) in RX mode, and 26-dB peak gain with 13.5-dBm 1-dB compression output power (OP $_{1\,\text{dB}}$ ) in TX mode. The core size of this proposed design is only 0.06 mm $^2$ which is only 20 $\%$ –50 $\%$ of the size occupied in prior works.

In this brief, we propose an efficient asynchronous parallel expected improvement matrix-based (EIM) constrained multi-objective optimization approach with mixed models for analog circuit sizing. In contrast to other asynchronous methods for single-objective optimization, our method aims to solve multi-objective problems with multiple constraints. The proposed new asynchronous strategy can parallelize not only circuit simulations but also the process of building models. We introduce an EIM criterion for objectives as the acquisition function and build radial basis function models for constraints. The proposed method is based on prescreening instead of internal optimization to further reduce the computational cost of models. Experimental results on two real-world circuits illustrate that when the batch size is 15, our proposed method provides with better trade-off information and reduces the total runtime of the optimization by up to 92X compared with NSGA-II. There is a speedup of up to 8X and 4X compared with the state-of-the-art synchronous approach and asynchronous approach in terms of the runtime.

A novel RF small-signal model in the form of a physics-based equivalent circuit for advanced bulk FinFETs is proposed. Based on the unique multifin structure, parallel resistance-capacitance branches are introduced to account for the gate-source and gate-drain admittances. The deembedding is carefully performed after its effectiveness is verified by accurately modeling the pad and interconnect parasitics. An analytical method is developed to directly extract the model parameters from measurements. The model is validated in 7 and 14 nm bulk FinFET technologies, and the modeled results show an excellent agreement with the measured data up to 50 GHz (~ fT/4). The dependencies of FinFET RF performances on the layout dimensions are investigated, and they are compared between the two advanced FinFET technologies.