Junjun Qiu

This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path.With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm². At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from - 234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions.

This article presents a 7-GHz fractional- N digital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a $-$ 62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm $^{2}$ area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of $-$ 247.4 dB.

This work presents a 6.5-to-8-GHz cascaded dual-fractional- $N$ digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer- $N$ mode and an integrated jitter of 190.8 fs in fractional- $N$ mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of $-$ 242.9 dB. The fractional spur at near-integer channel is as low as $-$ 52.79 dBc, and the reference spur is $-$ 72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm ² core area.

This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.

This article proposes a time-mode-modulation (TMM) digital quadrature power amplifier (PA), which can realize high power efficiency at power back-off (PBO) by applying the 1-bit delta–sigma modulator (DSM) and hybrid finite impulse response (FIR) filter. The 1-bit DSM and digital mixer encode the multi-bit baseband $I/Q$ input signal into a 1-bit signal for on/off controlling the 1-bit PA to realize the TMM operation. Capacitor arrays are not required in the proposed PA, and redundant power dissipation on charging the capacitor array in conventional switched capacitor PAs (SCPAs) is avoided. Furthermore, a hybrid FIR filter comprising a two-tap digital FIR filter and a two-tap transformer (XFMR) combined semi-digital FIR filter suppresses the DSM quantization noise (QN) to avoid efficiency degradation. The XFMR combined semi-digital FIR filter is insensitive to mismatches, which maintains the high linearity of the 1-bit TMM PA. The proposed TMM PA is fabricated in 65-nm CMOS. Without digital pre-distortion (DPD), it achieves 26.4% power-added efficiency (PAE) with 40-MSymbol/s 64-quadrature amplitude modulation (QAM) signal and 20.9% PAE with 20-MSymbol/s 256-QAM signal at 2.6 GHz.

This letter presents a 24–30-GHz variable gain amplifier (VGA) achieving low-phase variation in a standard RF 65-nm CMOS process. The proposed VGA employs two stages. Phase compensation during the gain variation is realized with the dynamic complementary phase variation at the first stage. The second stage is utilized to increase the gain and keep linearity. Measurement results prove that the proposed VGA achieves a continuous gain tuning range of 8.3 dB. Under this condition, low-phase variation is realized with the root-mean-square (RMS) phase error less than 3° from 24 to 30 GHz. Moreover, the RMS phase error is less than 2° at the desired 5G frequency band from 27.5 to 29.5 GHz. The peak gain is measured with 18.7 dB at 29 GHz. With the max gain setting, the measured OP _1dB and OIP ₃ are 5.1 and 9.3 dBm, respectively, and the measured noise figure is from 4.6 to 6.8 dB at the frequency range from 24 to 30 GHz.

This letter proposes a Sub-GHz digital polar power amplifier circuit, which is intrinsically linear and power-efficient. The architecture is based on a 1-bit Delta-Sigma Modulator (DSM) to achieve amplitude modulation without a lossy capacitor array, which improves efficiency. A deskewing circuit eliminates skew-induced non-linearity and improves the EVM without pre-distortion. The proposed 1-bit-DSM-based PA, integrated in a 65 nm CMOS process, achieves -36.5 dB RMS EVM and 24.1% PAE for a 10 MSymbol/s 1024-QAM modulated signal at 960 MHz carrier, without pre-distortion.

This paper demonstrates a compact BLE transmitter (TX) achieving fully on-chip integration and high system-efficiency. This BLE TX is constructed based on a 1.2 GHz 8-phases current-reused ring oscillator (RO) with a digital phase-locked loop (PLL). To mitigate the spurious emission, including HD2 caused by phase mismatches, an edge-timing calibration is proposed by reusing the digital PLL in this paper. A transformer-based Class-D PA with implicit LC-notch is implemented to improve the system efficiency with higher harmonic suppression for both HD2 and HD3 with a compact on-chip area. The presented TX supports both 1 Mbps and 2 Mbps GFSK modulation with low power consumption.

In this article, a $Ka$ -band satellite communication (SATCOM) transceiver is first presented using a standard CMOS technology. The proposed $Ka$ -band SATCOM transceiver consists of a high-linearity transmitter (TX) and dual-channel receiver (RX); both TX and RX are based on direct-conversion architecture. By implementing the dual-channel RX, multiple multiplexing modes, including polarization multiplexing and frequency multiplexing, can be enabled depending on the application. The RX variable gain is distributed in both RF blocks and baseband blocks to achieve a wide input dynamic range. The LNA employs a dual-coupling transformer for a low-noise figure (NF) and wideband input matching; moreover, it enhances the amplifier unilateralization characteristic to mitigate the loading effect from switched attenuators. An adjacent channel interference (ACI) cancellation scheme is proposed to further enhance the RX linearity in the frequency multiplexing mode. In the TX, single-turn high-quality-factor transformer is employed to realize matching network and four-way power combining. A prototype of the SATCOM transceiver is fabricated in a standard 65-nm CMOS process. Under 1.05-V supply voltage, the TX achieves a $P_{\mathrm {SAT}}$ of 20.5 dBm and an average output power of 12 dBm with 2% error vector magnitude (EVM) and a 37.6-dB ACPR. The dual-channel RX achieves an NF of 5.4 dB, an IIP3 of −30 dBm on the high-gain mode, the ACI cancellation is measured of 7.9 dB with a 100-MHz signal bandwidth.