Alexander Flasby

The aggressive scaling of electronic devices has brought ferroelectric materials to the forefront of nanoscale research, where lateral dimensions strongly influence switching dynamics and device performance. In this context, W/ Hf _0.5 Zr _0.5 O ₂ / p‐Ge capacitors with top electrode sizes ranging from 10 µm down to 0.1 µm are investigated using conductive atomic force microscopy (C‐AFM). Frequency‐dependent measurements reveal that peak switching currents ( I _sw ) increase with sweep rate, yet the total switched charge remains nearly constant, consistent with full polarization reversal in micro‐ and submicron devices. Positive‐Up‐Negative‐Down (PUND) analysis further isolates the switching current, allowing reconstruction of polarization–voltage ( P‐ ‐ V ) loops and quantification of remnant polarization. The smallest devices (0.01 µm ² ) exhibit switching currents below the detection threshold due to parasitic capacitance, masking intrinsic ferroelectric behavior. In contrast, submicron capacitors display an apparent increase of remanent polarization attributed to the larger perimeter‐to‐area ratio, emphasizing the role of edge‐dominated switching. Together, these findings establish C‐AFM as a powerful, spatially resolved technique for probing ferroelectric switching in realistic device geometries, providing essential insights for non‐volatile memory and neuromorphic applications.

Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.

Continuous gate sets are a key ingredient for near-term quantum algorithms. Here, we demonstrate a hardware-efficient, continuous set of controlled arbitrary-phase ( CZ θ ) gates acting on flux-tunable transmon qubits. This implementation is robust to control pulse distortions on time scales longer than the duration of the gate, making it suitable for deep quantum circuits. Our calibration procedure makes it possible to parameterize the continuous gate set with a single control parameter, the idle time between the two rectangular halves of the net-zero control pulse. For calibration and characterization, we develop a leakage measurement based on coherent amplification, and a new cycle design for cross-entropy benchmarking. We demonstrate gate errors of 0.7 % and leakage of 4 × 10 − 4 across the entire gate set. This native gate set has the potential to reduce the depth and improve the performance of near-term quantum algorithms compared to decompositions into CZ π gates and single-qubit gates. Moreover, we expect the calibration and benchmarking methods to find further possible applications.

When using unitary gate sequences, the growth in depth of many quantum circuits with output size poses significant obstacles to practical quantum computation. The quantum fan-out operation, which reduces the circuit depth of quantum algorithms such as the quantum Fourier transform and Shor’s algorithm, is an example that can be realized in constant depth independent of the output size. Here, we demonstrate a quantum fan-out gate with real-time feedforward on up to four output qubits using a superconducting quantum processor. By performing quantum state tomography on the output states, we benchmark our gate with input states spanning the entire Bloch sphere. We decompose the output-state error into a set of independently characterized error contributions. We extrapolate our constant-depth circuit to offer a scaling advantage compared to the unitary fan-out sequence beyond 25 output qubits with feedforward control, or beyond 17 output qubits if the classical feedforward latency is negligible. Our work highlights the potential of midcircuit measurements combined with real-time conditional operations to improve the efficiency of complex quantum algorithms.

Quantum computers will require quantum error correction to reach the low error rates necessary for solving problems that surpass the capabilities of conventional computers. One of the dominant errors limiting the performance of quantum error correction codes across multiple technology platforms is leakage out of the computational subspace arising from the multilevel structure of qubit implementations. Here, we present a resource-efficient universal leakage reduction unit for superconducting qubits using parametric flux modulation. This operation removes leakage down to our measurement inaccuracy of 7×10^{-4} in approximately 50 ns with a low error of 2.5(1)×10^{-3} on the computational subspace, thereby reaching durations and fidelities comparable to those of single-qubit gates. We demonstrate that using the leakage reduction unit in repeated weight-two stabilizer measurements reduces the total number of detected errors in a scalable fashion to close to what can be achieved using leakage-rejection methods that do not scale. Our approach does not require additional control electronics or on-chip components and is applicable to both auxiliary and data qubits. These benefits make our method particularly attractive for mitigating leakage in large-scale quantum error correction circuits, a crucial requirement for the practical implementation of fault-tolerant quantum computation.