Daxu Zhang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Daxu Zhang has a total of 19 co-authors. Here are the top co-authors by number of shared publications:
Duo Li
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications- Kenichi Okada
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications - Wenqian Wang
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications - Yuang Xiong
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications - Yuncheng Zhang
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications - Zezheng Liu
Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, Japan
3 shared publications
Latest Publications
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 9, 250-253
A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 9, 250-253
A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC
- Open Access
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (10) , 1-17
A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (10) , 1-17
Open AccessA Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration
- Open Access
- 23 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 60 (12) , 4633-4646
CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator
Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs into three-level signals using simple delta-sigma modulators (DSMs), followed by a nine-state lookup table (LUT) to directly generate amplitude modulation (AM) and phase modulation (PM) signals. The complex coordinate rotation digital computer (CORDIC) that is widely used in polar TXs is not required. The AM signal is truncated to two levels for on/off control of an intrinsically linear 1-bit power amplifier (PA). The PA avoids the linearity and switching loss issues of conventional switched-capacitor PAs (SCPAs). The PM signal is represented with 3 bits for eight-phase generation via edge selection from a $4\times $ carrier local oscillator (LO), which offers better linearity and power efficiency than phase modulators based on multi-bit digital-to-time converters (DTCs). Therefore, the proposed approach enables simultaneous improvements in power efficiency and linearity. Fabricated in a 65-nm CMOS process, the proposed TX achieves a 33.5% peak power-added efficiency (PAE) at 24.2-dBm output power and supports wideband 50-MSymbol/s 256-quadratic-AM (QAM) signals without digital predistortion (DPD). A maximum system efficiency (SE) of 24.5% is achieved at −25.1-dB error vector magnitude (EVM), demonstrating superior performance compared to state-of-the-art DPD-less digital polar TXs.
- 23 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 60 (12) , 4633-4646
Open AccessCORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator
Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs into three-level signals using simple delta-sigma modulators (DSMs), followed by a nine-state lookup table (LUT) to directly generate amplitude modulation (AM) and phase modulation (PM) signals. The complex coordinate rotation digital computer (CORDIC) that is widely used in polar TXs is not required. The AM signal is truncated to two levels for on/off control of an intrinsically linear 1-bit power amplifier (PA). The PA avoids the linearity and switching loss issues of conventional switched-capacitor PAs (SCPAs). The PM signal is represented with 3 bits for eight-phase generation via edge selection from a $4\times $ carrier local oscillator (LO), which offers better linearity and power efficiency than phase modulators based on multi-bit digital-to-time converters (DTCs). Therefore, the proposed approach enables simultaneous improvements in power efficiency and linearity. Fabricated in a 65-nm CMOS process, the proposed TX achieves a 33.5% peak power-added efficiency (PAE) at 24.2-dBm output power and supports wideband 50-MSymbol/s 256-quadratic-AM (QAM) signals without digital predistortion (DPD). A maximum system efficiency (SE) of 24.5% is achieved at −25.1-dB error vector magnitude (EVM), demonstrating superior performance compared to state-of-the-art DPD-less digital polar TXs.