Zezheng Liu

Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs into three-level signals using simple delta-sigma modulators (DSMs), followed by a nine-state lookup table (LUT) to directly generate amplitude modulation (AM) and phase modulation (PM) signals. The complex coordinate rotation digital computer (CORDIC) that is widely used in polar TXs is not required. The AM signal is truncated to two levels for on/off control of an intrinsically linear 1-bit power amplifier (PA). The PA avoids the linearity and switching loss issues of conventional switched-capacitor PAs (SCPAs). The PM signal is represented with 3 bits for eight-phase generation via edge selection from a $4\times $ carrier local oscillator (LO), which offers better linearity and power efficiency than phase modulators based on multi-bit digital-to-time converters (DTCs). Therefore, the proposed approach enables simultaneous improvements in power efficiency and linearity. Fabricated in a 65-nm CMOS process, the proposed TX achieves a 33.5% peak power-added efficiency (PAE) at 24.2-dBm output power and supports wideband 50-MSymbol/s 256-quadratic-AM (QAM) signals without digital predistortion (DPD). A maximum system efficiency (SE) of 24.5% is achieved at −25.1-dB error vector magnitude (EVM), demonstrating superior performance compared to state-of-the-art DPD-less digital polar TXs.

This article presents a 7-GHz fractional- N digital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a $-$ 62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm $^{2}$ area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of $-$ 247.4 dB.

This work presents a 6.5-to-8-GHz cascaded dual-fractional- $N$ digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer- $N$ mode and an integrated jitter of 190.8 fs in fractional- $N$ mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of $-$ 242.9 dB. The fractional spur at near-integer channel is as low as $-$ 52.79 dBc, and the reference spur is $-$ 72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm ² core area.

This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.

This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.

This article proposes a time-mode-modulation (TMM) digital quadrature power amplifier (PA), which can realize high power efficiency at power back-off (PBO) by applying the 1-bit delta–sigma modulator (DSM) and hybrid finite impulse response (FIR) filter. The 1-bit DSM and digital mixer encode the multi-bit baseband $I/Q$ input signal into a 1-bit signal for on/off controlling the 1-bit PA to realize the TMM operation. Capacitor arrays are not required in the proposed PA, and redundant power dissipation on charging the capacitor array in conventional switched capacitor PAs (SCPAs) is avoided. Furthermore, a hybrid FIR filter comprising a two-tap digital FIR filter and a two-tap transformer (XFMR) combined semi-digital FIR filter suppresses the DSM quantization noise (QN) to avoid efficiency degradation. The XFMR combined semi-digital FIR filter is insensitive to mismatches, which maintains the high linearity of the 1-bit TMM PA. The proposed TMM PA is fabricated in 65-nm CMOS. Without digital pre-distortion (DPD), it achieves 26.4% power-added efficiency (PAE) with 40-MSymbol/s 64-quadrature amplitude modulation (QAM) signal and 20.9% PAE with 20-MSymbol/s 256-QAM signal at 2.6 GHz.

This paper demonstrates a compact BLE transmitter (TX) achieving fully on-chip integration and high system-efficiency. This BLE TX is constructed based on a 1.2 GHz 8-phases current-reused ring oscillator (RO) with a digital phase-locked loop (PLL). To mitigate the spurious emission, including HD2 caused by phase mismatches, an edge-timing calibration is proposed by reusing the digital PLL in this paper. A transformer-based Class-D PA with implicit LC-notch is implemented to improve the system efficiency with higher harmonic suppression for both HD2 and HD3 with a compact on-chip area. The presented TX supports both 1 Mbps and 2 Mbps GFSK modulation with low power consumption.

Background and objectives The periarticular sacroiliac joint (SIJ) technique has become an important area of focus, and the quartering of the SIJ posterior ligamentous region has been proposed as a way to refine this technique. However, detailed nerve distribution combined with the division of the SIJ posterior ligamentous region is lacking. We aimed to explore the innervation of the SIJ posteriorly based on the quartering of the SIJ posterior ligamentous region. Methods Sixteen SIJs from eight embalmed cadavers were studied. Each SIJ posterior ligamentous region was equally divided into areas 0–3 from top to bottom. The origin, distribution, quantity, transverse diameter, spatial orientation, relation with bony structures, and the number of identifiable terminal nerve branches in each area were examined. Results Areas 0–1 were innervated by the lateral branches of the dorsal rami of L4−L5 directly in all specimens. Areas 2–3 were innervated by that of both lumbar and sacral nerves via the posterior sacral network (PSN), with L5 contributing to the PSN in all specimens and L4 in 68.75%. The number of identifiable terminal nerve branches were significantly higher in areas 2–3 than in areas 0–1. Conclusions The inferior part of the SIJ posterior ligamentous region seems to be the main source of SIJ-related pain and is innervated by lumbar and sacral nerves via the PSN. However, the superior part directly innervated by lumbar nerves should not be neglected, and further clinical verification is needed.