Ruben Asanovski

The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.

investigate the origin of negative threshold voltage shifts in back-gated amorphous IGZO TFTs under positive bias and high temperature stress. Combined DC and 1/f noise measurements reveal that the stress does not generate new dielectric traps but instead broadens the IGZO conduction band tail states. A recovery experiment confirms that the associated threshold voltage, subthreshold swing, and noise degradation are reversible. Simulations using an in-house Poisson solver confirm the experimental observations that high-temperature stress increases hydrogen doping and the density of sub-gap states.

The realization of practical, large-scale quantum computers requires the optimization of classical electronics for cryogenic operation to solve the interconnect bottleneck between quantum processors and control electronics. Devices from Fully-depleted Silicon-on-insulator (FDSOI) technology nodes are ideal for cryogenic operation due to the possibility of tuning the threshold voltage through the back-gate and reducing power consumption. However, they must be assessed in terms of not just their performance but also their reliability at conditions of interest. In this study, we present the Bias Temperature Instability (BTI) characteristics of commercial 22 nm FDSOI transistors optimized for low-power applications at temperatures ranging from 300 K down to 4 K, focusing on the impact of stress time and gate overdrive voltage. We observe that BTI remains active in both pMOS and nMOS at 4K with weak dependencies on stress magnitude and duration. Crucially, recovery from threshold voltage shifts is also slowed down at cryogenic temperatures.

Accurate determination of thermal resistances having a clear physical interpretation is crucial for analyzing self-heating effects (SHEs) in bulk FinFETs and ensuring reliable circuit operation. In this article, we use extensive electrothermal simulations, calibrated against experiments, to validate a popular method to monitor SHEs based on the measured AC output conductance. The results confirm that nanoscale silicon fins exhibit degraded thermal conductivity compared with the bulk silicon case. Then, we explore the relationship between the temperature extracted by the output conductance method and the maximum temperature inside the fin (which is a useful parameter to study device reliability) as a function of device bias and dimensions, providing a few projections toward scaled technology nodes. Our results show that the following hold: 1) the overtemperature extracted with the AC output conductance method represents an average overtemperature across the device active area and 2) the AC conductance method largely underestimates the peak temperature of long-channel devices; less so for short-channel ones. In this latter case, however, the difference between the above temperatures changes appreciably as a function of gate voltage.

This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/ f noise characterization and advanced modeling. This research demonstrates that MOSFETs with gate-stacks treated with atomic hydrogen (H*) and oxygen (O*) ( T $<$ 450 $^{\circ}$ C) yield 1/ f noise levels comparable to those of high-thermal budget devices. We also demonstrate that the noise of both pMOSFETs and nMOSFETs mainly originates from defects in the SiO2 interfacial layer (IL). In addition, accurate modeling of 1/ f noise provides useful insights into the dielectric defect densities before and after passivation. Notably, the contribution of O-vacancies in HfO2 to 1/ f noise appears negligible, whereas it is very important for positive bias temperature instabilities (PBTIs). The results confirm the effectiveness of H* and O* treatments in reducing the electrically active dielectric defects while contributing to a better understanding of the underlying passivation mechanisms.

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ${T}$ ), referred to as “excess 1/f noise,” observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.